The present invention relates to the fabrication of integrated circuits, and more particularly to reticles (masks) used during the fabrication of integrated circuits.
Integrated circuit (IC) design typically utilizes computer simulation tools to help create a circuit schematic, which typically includes individual devices that are coupled together to perform a certain function. To actually fabricate an IC that performs this function, the circuit schematic must be translated into a physical representation known as a layout using computer-aided design (CAD) tools. The layout translates the discrete circuit elements of the circuit schematic into shapes that are used to construct the individual physical components of the circuit, such as gate electrodes, field oxidation regions, diffusion regions, and metal interconnections.
CAD tools that generate the layout are usually structured to function under a set of predetermined design rules in order to produce a functional circuit. These design rules are often determined by certain processing and design limitations defined by the particular IC fabrication process to be used, such as design rules defining the space tolerance between devices or interconnect lines that prevent undesirable interaction between devices or lines. Design rule limitations are frequently referred to as critical dimensions. For example, a critical dimension of a circuit is commonly defined as the smallest width of a line or the smallest space between lines that can be supported by an IC fabrication process. Consequently, the critical dimension determines the overall size and density of the IC.
The layout is optically transferred onto a semiconductor substrate using a series of lithographic reticles (masks) and an exposure tool. Photolithography is a well-known process for transferring geometric shapes (mask pattern portions) present on each reticle onto the surface of a semiconductor substrate (e.g., a silicon wafer) using the exposure tool (e.g., an ultra-violet light source). In the field of IC lithographic processing, a photosensitive polymer film called photoresist is normally applied to the wafer and then allowed to dry. The exposure tool is utilized to expose the wafer with the proper geometrical mask patterns by transmitting UV light or radiation through the reticles. After exposure, the wafer is treated to develop the mask images transferred to the photosensitive material. These masking images are then used to create the device features of the circuit.
An important limiting characteristic of the exposure tool is its resolution value. The resolution value for an exposure tool is defined as the minimum mask pattern feature that the exposure tool can repeatedly expose onto the wafer.
FIG. 1 is a perspective view showing a simplified conventional reticle 100 that is being used during the optical transfer of an integrated circuit portion onto a semiconductor substrate 110. Reticle 100 includes an opaque masking material (e.g., chrome) that is deposited on a transparent substrate 102 and etched to form a lithographic mask pattern 105. During an integrated circuit fabrication process, ultra-violet (UV) light or radiation emitted from an exposure tool (not shown) is transmitted through reticle 100, thereby forming an image 112 of mask pattern 105 on semiconductor substrate 110. As indicated by the tapered dashed lines in FIG. 1, the lithographic process typically utilizes an optical reduction system such that image 112 is substantially smaller than (e.g., ⅕) the size of lithographic mask pattern 105. Note that the resolution values of mask pattern 105 are indicated as a width W of a mask pattern portion 106, and a space S between mask pattern portion 106 and mask pattern portion 107. Width W and space S represent the smallest dimensions that can be repeatedly transferred onto semiconductor substrate 110 by the exposure tool, and produce structures meeting the critical dimensions defined by the IC fabrication process.
FIG. 2 is a plan view showing a portion of reticle 100 in which some of the masking material has melted and formed a bridge 210 between mask pattern portions 106 and 107, thereby generating flaws in the IC formed on semiconductor substrate 110 (see FIG. 1).
Space S continues to decrease as improved stepper designs have allowed the resolution values of fabrication processes to decrease, thereby increasing the likelihood of charge transfer between portions 106 and 107. Eventually, as is being experienced with state-of-the-art fabrication processes, the combination of charge stored in mask pattern portions 106 and 107 and the small space S separating these portions results in melting of the masking material to form bridge 210.
What is needed is a structure and method that prevent bridging of the masking material between adjacent portions of the mask pattern, thereby facilitating the development of fabrication processes that define smaller resolution values.
The present invention is directed to a reticle that is modified to prevent bridging of the masking material (e.g., chrome) between adjacent portions of the lithographic mask pattern during an IC fabrication process. As described above, this bridging effect is caused when dissimilar charges that are generated in adjacent mask pattern portions cause the masking material to melt and flow between the mask pattern portions. The present invention prevents bridging by either equalizing or minimizing these dissimilar charges, thereby reducing the potential between adjacent portions below that required to melt the masking material to form undesirable bridges. Accordingly, the present invention facilitates the development of fabrication processes that define ever-smaller resolution values.
According to a first aspect of the present invention, a reticle is modified to provide electrical connections between the various portions of the lithographic mask pattern, thereby balancing dissimilar charges generated in the portions during fabrication processes.
In one embodiment, sub-resolution wires are provided between the mask pattern portions to balance dissimilar charges. The sub-resolution wires are less than the resolution value of an associated exposure tool, and therefore do not generate lithographic features on the underlying semiconductor substrate during the fabrication process. When dissimilar charges are generated in adjacent mask pattern portions, a current is generated in the sub-resolution wire extending between the mask pattern portions, thereby preventing bridging of the masking material by balancing the dissimilar charges.
In another embodiment, a method for generating the reticle having sub-resolution wires includes combining data defining the lithographic mask pattern with frame data defining a grid of intersecting sub-resolution lines. A lithographic mask pattern is then formed on a surface of the reticle using the combined data according to known techniques. The combined lithographic pattern includes at least one sub-resolution wire extending between adjacent mask portions such that, when dissimilar charges are generated in the adjacent mask pattern portions during the fabrication process, current flows through the sub-resolution wire to equalize the charges.
In another embodiment of the present invention, a transparent conductive film is formed under or over the lithographic mask pattern to balance dissimilar charges that are generated in adjacent mask pattern portions. Because the conductive film (e.g., Indium-Tin Oxide (ITO) or Molybdenum Silicide (MoSi) less than 50 angstroms thick) is transparent, it does not generate lithographic features on the underlying semiconductor substrate during the fabrication process. When higher frequency radiation is used to expose the photoresist, mask materials may be different, for example when x-ray radiation is used, tantalum may be used for forming the opaque pattern regions and aluminum for forming the transparent conductive regions. When dissimilar charges are generated in adjacent mask pattern portions, a current is generated in sections of the transparent conductive film extending between the mask pattern portions, thereby preventing bridging of the masking material by balancing the dissimilar charges.
In accordance with a second aspect of the present invention, a reticle is modified to break elongated portions of the lithographic mask pattern into relatively small segments that are separated by sub-resolution gaps. The sub-resolution gaps are less than the resolution value, and therefore do not generate lithographic features on the underlying semiconductor substrate during the fabrication process. In other words, the lithographic image formed on the underlying semiconductor substrate is a continuous elongated structure that is not separated into segments. By separating the elongated portions into smaller segments on the reticle, the amount of charge generated on each segment is minimized, thereby reducing the potential between adjacent portions of the lithographic mask pattern and preventing bridging of the masking material.
In another embodiment, a method for generating the reticle having elongated mask portions separated by sub-resolution gaps includes combining data defining the lithographic mask pattern with data defining a grid of intersecting sub-resolution grooves. A lithographic mask pattern is then formed on a surface of the reticle using the combined data according to known techniques. Each elongated portion of the combined lithographic pattern is separated into at least two segments by a sub-resolution gap, which is part of one of the grooves, such that the segments are electrically isolated.
The present invention will be more fully understood in view of the following description and drawings.